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3D structure Implementation: A Survey

M. H. Jabbar, D. HouzetGIPSA Lab, Grenoble INP, France


research in 3D integration has been attracted researchers from industries in addition to academics because of its advanced merits over 2nd structure comparable to greater efficiency, lessen vigour consumption, small form element and assist for heterogeneous know-how integration. Depth knowing about 2d and 3D architecture is terribly essential earlier than true 3D design is taking place. in this paper, we talk about the analysis works on 3D integration notably its advantages when evaluating with CMOS scaling going to sub-nanometer process know-how. We also describe a few 3D architecture implementation up to now developed to justify the want of our 3D experimental implementation which is presently being developed in accordance with an extended collaboration between ENSTA and GIPSA-Lab on multimedia MPSoC design.


in line with the overseas expertise Roadmap Semiconductor (ITRS) the variety of processing facets is anticipated to raise greater than one hundred processors [1]. moreover, the reminiscence measurement is additionally projected to raise dramatically in the future along with the increasing variety of processing features. New concept of electronic design has been added a couple of years lower back which is 3D integration. This expertise allow building circuits in 3 dimensional (3D) structures with the aid of stacking the wafers or dies in a number of layers the usage of TSV for inter tier connection, as oppose to typical 3D stacking components the usage of wire bonding. This new know-how offers a few benefits which could raise the gadget density permitting complex design implementation and tremendously growth performance. The intention of this paper is to provide everyday introduction of 3D integration expertise and discuss the choice between CMOS scaling and 3D stacking. We additionally current a couple of implementations of 3D architecture said up to now and talk about their functions.

II. TSV know-how

TSV is a method that uses via throughout different layers of energetic silicon. material uses for TSV is Copper Tungsten (W) [2] [3] , Copper (Cu) [4] [5] and Poly-Silicon (Poly-Si) [6]. Poly-Si cloth is stable and has much less impact on machine characteristic than other materials. besides the fact that children, Cu or W is extra correct for the TSV due to reduce resistance. Cu is most generic since it has good thermal conductivity in comparison to W and Poly-Si. W has longer delay compared with Cu TSV for any diameter size [7].

TSV allows excessive interconnection density between stacked chips. for instance one hundred twenty,000 interconnections for 12.5 mm2 area of 3D chip containing processor and memory [8]. a different reported work obtain 103 interconnections for W TSV with 10 μm TSV pitch in the enviornment of 1 mm2 [9]. yet another critical element is TSV lining or TSV insulation to insulate from the Silicon substrate. Most familiar material is Silicon Oxide which can also be deposited using Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).


As for CMOS transistor scaling, a number of essential issues exists as follow:

  • growing to be fabrication can charge: non-ordinary engineering (NRE) expenses and lithography cost is expanding in opposition t smaller feature size.
  • giant effect of process model: relocating towards smaller transistor dimension, system and parameter model is worsening. numerous new options are obligatory for mitigating the effect of process version for forty five nm expertise node in comparison with the previous know-how [10]. as an example, amongst scaling challenges past 32 nm expertise are [11]:
  • expanded off-state current from degraded drain-prompted barrier reducing drain result in leakage current (DIBL) and subthreshold slope (SS) by using poorer brief channel results significantly limits the constructive gate length shorten than about 15 nm.
  • lowering oxide thickness, tox gives more desirable channel handle but with the penalty of increased gate leakage existing and elevated channel doping, at last decreased mobility and raises random dopant fluctuations (RDF) and degrading minimal working voltage.
  • Interconnect wire lengthen develop into greater massive than gate prolong and in consequence boost world lengthen. for this reason, performance improvement is slowly accelerated. It as a consequence raises energy consumption [12].
  • In 3D integration, the long interconnect wire size is decreased to square root of the length in 3D integration as a result of the stacking. This improves the velocity where it reduces the RC extend of the interconnect wire and also in the reduction of the number of buffers along the interconnect wire. for instance discount on ordinary in total wire size is greater than 28% when stacking two to 5 wafers and from 31% reduction for the longest wire for overseas Symposium of actual Design (ISPD’ninety eight) circuit benchmarks [13]. as the interconnect wire length is reduced, its capacitance is decreased, the number of repeaters along the interconnect wire is hence reduced and eventually vigor consumption is reduced as well. 3D integration additionally supports integration of heterogeneous technology corresponding to digital, analog, RF and MEMS technology the place they can also be technique in keeping with their technique and then stack with different expertise. finally 3D integration introduces small kind component which is very appropriate for cell instruments.


    The magnitude effect of stacking in 3D structure is elevated peak temperature [14] [15] [16]. The temperature within the chip can attain greater than a hundredºC. Temperature adaptation between dies may also be round 10ºC for two stacked dies [17]. Hotspot within the 3D chip can also be up to more than a hundredºC whereas temperature change between stacks will also be 1-20 ºC [18]. Two things are very critical in consequence from this extreme temperature which is temperature model and hotspot which affect the reliability of the chip are mean time to failure ratio (MTTR) and time to breakdown (TTBD).

    several methods had been proposed for thermal management strategies to clear up thermal issue in 3D integration corresponding to thermal herding which vicinity probably the most frequently swap blocks near to the warmth sink [19], the usage of thermal vias to switch warmth out of the chip [20] [21] [22] and thermal conscious design that focusing physical design stage akin to floorplan and placement [23] [24] [25]. Thermal administration innovations the usage of dynamic frequency scaling (DFS) proposed that dies near heat sink can be assigned using greater frequency (finally bigger temperature) whereas workload that has powerful thermal have an impact on is assigned to the die that has more desirable cooling efficiencies [17] .

    Thermal stress is one more effect of thermal difficulty when integrating the use of TSV. here's due to the diverse CTE property of Silicon, Cu, Silicon Dioxide and W. The CTE of Cu is greater than W when examine with Silicon which ability that Cu TSV has better stress have an impact on on Silicon. youngsters, W has reduce thermal conductivity than Cu. Thermal stress trigger timing edition around ±10% for an individual cellphone [26]. Thermal brought about stress in 3D integration causes crack at the interface of TSV and Silicon substrate and between Cu interconnects and low-k insulator [27]. This impact is strongly influent on machine reliability. Cu TSV produces high thermal stress up to 750 MPa.

    additionally, there are lots of challenges for trying out 3D architecture such as examine architecture, test access mechanism, check scheduling, test pattern, checking out under thermal and vigor constraint which is vital specifically for checking out at run time. New defects create throughout 3D integration system delivered new category of defects reminiscent of in TSV or bonding constitution which require diverse testing techniques. testing for 3D architecture is a fine challenge as a result of functional instruments of processors at micro architectural level may also be partitioned at a couple of layer. testing is complicated because every layer doesn't have a complete useful equipment and for this reason require new testing method. furthermore, pre-bond and publish-bond testing is also a must-have to make certain only prevalent good die (KGD) is built-in within the 3D structure and TSV formation as well as bonding constitution don't have defects [28].

    V. 3D architecture IMPLEMENTATION

    We focus on a number of 3D chips which have been taped out for diverse purposes over the last few years. There are different 3D chip have been fabricated devoid of the use of TSV akin to [29] and it is not mentioned right here.

    In [30], they designed sixty four cores the use of two tiers Tezzaron know-how and international Foundaries 130 nm regular cells. The Tezzaron technology makes use of by way of first formulation with face to face bonding wafer level stacking. They created customized VLIW in-order processors in 5 tiers pipeline architecture to have efficient vigor productive inter core verbal exchange by way of removing significant and sophisticated facts structure. The undertaking demonstrated large memory bandwidth of 3D stacking architecture which is as much as 63 Gb/s. Inter core communique is achieved the usage of 4 buffers architecture in each core to their neighbouring cores. world barrier turned into used for synchronization for cores. The design can be run at 277 MHz. The design has been demonstrated with a number of parallel benchmarks proving the appropriate performance. each processor core has 1.5 KB guide memory and four KB records reminiscence. TSV structure has 1.2 um diameter, 5 um pitch, 6 um depth, tungsten TSV. Microbumps structure has three.4 um diameter and 5 um pitch. TSV is used for chip I/O interface and tier to tier connection is the use of microbumps. each and every tier has 5 mm x 5 mm silicon enviornment. A customized structure is created modified from JTAG IEEE 1149.1 for off chip interface which might be look at various handle state computer, and through the use of four pair of tdi and tdo for every four blocks, sixteen cores per block.

    In [31], they successfully tested 3D mesh NoC in 3 x 3 x three configuration using by way of remaining components from MIT Lincoln Lab 180 nm know-how FDSOI manner with 1.5 V. The 3D NoC is 2 mm x 2 mm per tier. The MIT Lincoln Lab has 3 metal layers for every tier, with a metal layer between two good tiers and a steel layer on proper of the complete stack. Its TSV architecture has 2.5 um x 2.5 um with three.9 um pitch. the two bottom tiers are bonded face to face and the third tier is connected the usage of face to again. The NoC used XYZ routing algorithm. each and every router port has 2 unidirectional hyperlinks with 16 bit links. there's a useful unit linked to each and every router designed the usage of linear feedback shift register (LFSR). The design become routed with 145 MHz with the vigor consumption of 120.5 mW. The purpose of the verify chip is to validate the high stage gadget simulator for 3D NoC they are working on. The router used adaptive xyz routing algorithm. The node is designed so simple as feasible so that huge network may also be implemented. The router has no reminiscence buffer and therefore each and every flit takes one cycle to travel across each and every router.

    one more 3D implementation is 3D FFT processor of 1024-aspect memory on logic for artificial aperture radar (SAR) using MITLL one hundred eighty nm FDSOI expertise [32]. The FFT is radix-2 Cooley-Tukey FFT. The chip confirmed that 3D architecture 53% reduce in commonplace wire length, 24% increase in optimum working frequency and 25.3% cut back within the total silicon area. The 3D die enviornment is 23.40 mm2, four.8 mm x four.eight mm. The design run at seventy nine.4 MHz, 12.6 ns with 409.2 mW power consumption at that pace. They used block stage partitioning, where processing points and reminiscence is placed in the three tiers such that memories is close the processing features.

    In [33], they carried out two tiers logic of two.5 mm x 5 mm with a three layer 8-channel 3D DRAM stacked on accurate the use of Tezzaron 3D technology with global Foundaries one hundred thirty nm technique 1.5 V. The goal is to show the feasibility of 3D IC architecture for SoC design. The partitioning scheme is completed manually at block level where USB controller, H.264 encoder block with its local reminiscence is positioned in suitable tier and different blocks in bottom good judgment tier, which AHB system bus connects between each good judgment tiers. The design run at 60 MHz and the DRAM can run at 133 MHz.

    In [34], they tested the feasibility of 3D NoC in 3D know-how in two tiers implemented the usage of die to wafer bonding of IMEC one hundred thirty nm procedure with one poly and two metal layers. The design has 1 mm2 die area with a hundred TSVs and 12 IO pads. The Copper TSV diameter is 5 um, 25 um depth and 10 um pitch inserted after FEOL and before BEOL formation. each tier has a site visitors generator, a slave reminiscence, a 3x3 switch and a JTAG controller and with fault tolerant verify buildings. The traffic generator is programmed the usage of JTAG controller which could send and receives flits from NoC. A slave reminiscence is sixty four bit arranged in 8 words large eight bit. Vertical links are unidirectional for the router and targeted for static faults like caught at and caught open fault. The design can run at 25 MHz at 0.four-1.5 voltage provide synchronously. every vertical link changed into implemented the usage of 2 TSVs for fault tolerant mechanism.

    In [35], the design of 32 bit 3D adder (Kogge- Stone) and 32 x 32 3D multiplier (Wallace Tree) were applied using MITLL a hundred and eighty nm 3D FDSOI expertise to exhibit the development of arithmetic circuits in 3D structure. The chip enviornment is 1.3 mm x 1.3 mm die area operating at 200 MHz in line with put up area and route timing estimation. The TSV size is 3 um x three um diameter and ~7 um depth. The 3D adder confirmed as much as ~34% and ~forty six% for velocity development and vigour discount whereas the 3D multiplier showed ~14% and ~7% of velocity growth and power discount from simulation outcome because the fabricated chip is just used to prototype the conception and 3D design circulate.

    In [36], 3D SRAM is designed the use of MITLL 180 nm FDSOI technique showing 32% improvement of entry time measured the use of lengthen-locked loop (DLL) as a result of the reduced observe-line wire in 3D structure. The TSV measurement is 2.5 um x 2.5 um. The 3D SRAM has 16 x sixteen mobile array in each tier with note line split partitioning became used for the implementation. The design is demonstrated at quite a number 70 - one hundred thirty MHz to calculate the access time. The outcomes of the dimension showed that 40 – 60 ps higher from the simulated influence.

    In [37], the LDPC (low density parity verify) was applied using 3 tier MITLL a hundred and eighty nm process in 6.3 um x 6.four um die enviornment. The design runs at 128 MHz achieving a throughput of two Gb/s with 430 mW energy consumption. The 3D implementation shown tremendous development in terms of wire length, clock skew, area and buffer size over its corresponding 2d implementation. at last the 3D reminiscence on reminiscence architecture implemented in 2.9 mm x 2.0 mm chip the usage of Tezzaron two tier expertise with international Foundaries one hundred thirty nm know-how confirmed quickly checkpointing and fix functions in 3D structure [38]. every sram tier has 1Mbit means built in sixty four banks, every financial institution has 256 phrases and 64 bit extensive. The chip can perform checkpointing/restart at 4k/cycles with 1 GHz velocity.

    The abstract of the previous 3D architecture implementation is proven in table 1 . To extra examine the 3D structure, we're at present designing sixteen processors in 2 tier using Tezzaron 3D technology. each and every tier has 8 processors related the use of 4x2 mesh NoC. We use open supply processor which is with ease accessible and we design a 3D router and community interface. The processor related to the community interface using elementary FIFO based communication for both facts and synchronization. The intention is to measure 3D NoC performance in precise chip by way of operating a couple of multimedia functions. We desire also to study parallel implementation in 3D NoC structure.


    3D integration know-how is at present under lively research by many businesses and greater analyze and investigation is needed in particular within the design exchange off between its benefits and disadvantages. This paper summarized in everyday about 3D integration masking how 3D overcome scaling issues and what are the considerations and challenges concerning it. We also described a couple of 3D chips implemented the usage of distinct system with different purposes. The aim is to provide generic however detail analysis that comprises all facets of 3D IC design.

    desk 1: abstract of 3D structure

    paintingsarchitecture / goal expertise / number of tier [30] 3D multicore (64 core) / to display large reminiscence bandwidth 130 nm / 2 tier [31] 3D mesh NoC with traffic gen. / to reveal working 3D NoC one hundred eighty nm / 3 tier [32] 3D FFT processor / show 3D benefit of velocity improvement and area discount180 nm / three tier [33] 3D SoC for H.264 / demonstrate 3D SoC architecture 30 nm / 5 tier (2 tier for common sense, three tier DRAM) [34] 3D mesh NoC (single switch) with site visitors gen. / display feasibility of 3D NoC a hundred thirty nm / 2 tier [35] 3D adder and 3D multiplier / demonstrate arithmetic circuit development in 3D180 nm / three tier [36] 3D SRAM / reveal reminiscence entry time growth in 3D180 nm / 3 tier [37] 3D LDPC decoder / demonstrate 3D architecture merits (wirelength, clock skew, area) one hundred eighty nm / three tier [38] 3D SRAM / exhibit quick checkpointing and restoration utility of difficult disk drive130 nm / 2 tier


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    [32] T. Thorolfsson, okay. Gonsalves and P. D. Franzon, Design automation for a 3DIC FFT processor for artificial aperture radar: A case examine, Design Automation convention, 2009. DAC '09. forty sixth ACM/IEEE, 2009, pp. fifty one-fifty six.

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    [34] I. Loi, P. Marchal, A. Pullini and L. Benini, 3D NoCs - Unifying inter and intra chip communication, Circuits and programs (ISCAS), court cases of 2010 IEEE foreign Symposium on, 2010, pp. 3337-3340.

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    keywords – 3D IC, 3D NoC, MPSoC, survey


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