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C4090-460 V2 test

IBM V2 test

IBM V2 test :: Article Creator

Embedded Symmetric MultiProcessing equipment on a SoC with 1.6GHz PowerPC IP in 45nm

via Gerard Boudon, IBM Microelectronics

abstract:

because the dimensions of lithography are actually closer to the simple physical limits, scaling is more and more difficult and accordingly multi-core processor options are only becoming extra normal within the embedded area. This paper describes in details the aspects that permit SoCs to be developed with up to eight 1.6 GHz PowerPC CPU cores in an embedded device aiding Symmetric Multiprocessing (SMP) structure. The balancing between CPU execution speed, reminiscence bandwidth and latency, and coherency overhead has been the objective of the design of the PLB6 and the L2 Cache IP's, to in the reduction of as a good deal as possible the drop-off in performance-per-core inherent in an SMP strategy.

1. Introduction

In September 2009, [1] IBM has added an 1.6 GHz PowerPC CPU IP in 45nm SOI - three.6mm2 measurement - that can also be integrated in multi-core gadget-on-chip (SoC) product families for communique, storage, consumer, and aerospace and defense embedded functions.

2. PowerPC476 IP

The PowerPC 476FP embedded processor core is a 5- subject, 5-pipeline, superscalar, 32-bit reduced instruction set laptop (RISC) processor. The core helps the vigor instruction Set structure V2.05. The core also supports reminiscence coherency to develop ASIC options into multiprocessing system environments and to raise its scalability.

The usual corporation of the processor core is shown on figure 1 .

guide path

The PowerPC 476FP processor is a excessive performance core with potential to situation up to five-guidelines per cycle. These guidance can feed in parallel the following five mounted element gadgets as neatly because the separate floating-point (FP) pipeline:

  • department pipeline
  • Load and shop operations
  • elementary arithmetic and logical operations
  • standard and sophisticated guideline pipeline,
  • Multiplication and division pipeline
  • L1 Cache

    The L1 32 KB guide and L1 32 KB information caches are two-cycle pipelined cache accesses, with index of real tackle within the 1024-entry unified translation lookaside buffer (UTLB)

    The L1 Cache tackle and records Caches are snoopable. Early delivery of guidelines to the floating-factor unit is enabled as a result of all directions are predecoded

    Floating-factor Unit

    The floating-point unit (FPU) is a pipelined, doubleprecision math computation processing unit it truly is attached to the processor core. The FPU conforms to the IEEE average for Binary Floating-point Arithmetic. The FPU is a Six-stage super-pipelined floating-point arithmetic execution with unbiased floating-aspect load-and-keep and execution instruments

    figure 1: PowerPC476 CPU core block diagram

    energy Saving

    The PPC476FP comprises design points to reduce the working power of the PowerPC 476FP

  • All latches are clock gated in order that idle services do not waste power.
  • All non executing and idle capabilities are disabled.
  • Static random entry memory (SRAM) is partitioned so that handiest the mandatory memory zone is enabled or chosen.
  • Doze and idle sleep modes can be found.
  • The valuable good judgment and the floating-point unit have separate clock makes it possible for
  • three. L2 Cache

    The L2 Cache IP [2] can also be configured in 256K, 512KB or 1 MB with a maximum of four,096 entries. The L2 cache line is 128 byte and the cache is four means set associative. To guide the excessive RAS (Reliability and Serviceability) requirement of the networking software, the L2 Cache arrays are included via Parity and ECC bits.

    IP measurement (bits) coverage L2 Cache 4,096x128x8x4 ECC Cache Tag four,096x36x4 ECC LRU four,096x30 Parity

    table 2 : SRAM array interior a 1MB L2 Cache IP.

    determine 2: SMP implementation with the PPC476 displaying L2 Cache states

    four. PLB6

    The 476FP “subsystem” which comprises the PowerPC 476FP CPU core, the stage 2 cache/cache controller, is related to different “subsystems” during the PLB6, the latest architectural extension of the CoreConnect native bus structure. This structure permits SoC designers to readily and impulsively increase total households of items, scaling the variety of “grasp” cores from 1 to sixteen (including 1 to eight Coherent CPU cores) on the bus. The PLB4 CoreConnect inside Bus is a shared bus of 128bit information at a maximum pace one fourth of the CPU velocity. It become designed for sub 1GHz CPU cores. high performance is carried out with a twin bus constitution one bus with a high throughput and the second with low latency. each of them is independently able to coping with study and write operations on the identical time.

    the brand new IBM CoreConnect PLB6 bus appears greater like a fabric with high velocity factor to point links, with each of them having 128 bit read and 128 bit Write statistics paths at one half of the CPU clock velocity.

    The bus fabric on the PLB6 is able to helping as much as 8 coherent grasp features, giving SoC designers the flexibleness to mix and in shape I/O masters, processors and different accelerators within the fabric.

    The excessive throughput of this bus is due to its fabric structure with up to eight slave segments, that may concurrently acquire or transmit records.

    every slave phase may additionally have as much as four slaves. it's viable, in 45nm know-how and without any preplacement in silicon, to operate the bus constitution at up to 800MHz.

    figure three: grasp and Slave attachments to the PLB6 CoreConnect bus

    Symmetric Multiprocessing (SMP)

    to be able to guaranty coherency between statistics in main memory and data in the a number of caches, the design of a standard SMP system is following the MESI protocol:

  • M Modified
  • E exclusive
  • S Shared
  • I Invalid
  • These states are associated with each and every cache line (L2 for the PPC476). every CPU performs snooping operation where these cache states are used. notice that the cache within the SMP processors architecture should have the same Cache line dimension and the same MESI states.

    The performance of such coherent SMP system is proscribed by using the incontrovertible fact that transactions are viable only between the Cache and the main reminiscence. as an instance, when a CPU 1 desires to examine a knowledge it's in a M (Modified)

    state in the cache of a CPU2, the primary operation is for the CPU2 to jot down the statistics in the reminiscence, after which the CPU1 can examine it. influence; 2 operations with 2 memory access are crucial for CPU1 to get the statistics.

    With the symmetric multiprocessing structure, scaling up the variety of processors, is efficient if at the equal time the hardware coherency is smart ample to handle the big bandwidth demand of the coherence transactions.

    it is critical to have a non-blocking off coherence resolution which prevents stopping CPU execution many of the time; within the PPC476 three additional states are delivered in the L2 cache in an effort to permit Cache to Cache switch, and improved Atomic operations.

    The information transfer is eased by way of a dedicated course between diverse subunit referred to as Intervention statistics direction. These 3 states are:

  • MU Modified Unsolicited
  • T Tagged
  • SL Shared ultimate
  • Intervention

    The intention of intervention by means of a CPU master is to reduce the latency obligatory to fetch a cache line when it is not existing in its L2, but is present in other L2’s.

    The SL (Share remaining) state is used for Intervention. It designate one (only) cache liable to supply the statistics after an intervention. As influence of an intervention among L2’s, Cache to Cache transfer is executed instead of memory access after a L2 leave out.

    5. illustration of SoC implementation

    An example of system implementation is proven in figure 4. The PLB6 is certainly reserved for high velocity access and for coping with memory coherency because of using numerous CPU cores. The gadget memory is also attached to the PLB6 because quick access to memory is terribly vital for running code and gives statistics now not already in cache. due to excessive velocity of the CPU it's crucial to provide information from leading reminiscence at a speed that handiest the late era of DDR3-1600MHz SDRAM can give.

    A SoC requires also excessive velocity I/O’s, which are connected here beneath a PLB6 to PLB4 interface. These I/O are often PCI categorical with 2d era 5gbps per port throughput. Legacy Ethernet is additionally obligatory since it is vital at the least to load code in the gadget. other IP blocks corresponding to USB or SATA can also be linked via an AXI bus as an example.

    figure 4. instance of SoC according to the PPC476 IP

    6. genuine implementation

    SOI: as a way to in the reduction of vigour and electrical leakage, the alternative of 45nm silicon-on-insulator (SOI) know-how was made. SOI can provide up to a 30 % chip performance improvement and 40 % vigor discount, compared to typical bulk silicon expertise [3]. This technology is used by IBM in a wide array of application-specific integrated circuits (ASIC) and foundry valued clientele as well as in chips for its servers and storage products.

    For efficiency and power dissipation optimization, the PowerPC476FP CPU IP has been designed in a hard core, whereas for flexibility in personalization, L2 cache and PLB6 are synthesizable; see layout of the PPC476 core on determine 5. right here table suggests quite a few areas of the IP block vital to build an SMP equipment.

    IP lengthPPC476 tough Core IP three.6 mm2 L2 Cache delicate IP 4mm2 * PLB6 cntl soft IP 0.035mm2 **

    * 512 KB L2

    ** Masters 4 C + 1 - Slaves 1C + 2 (C=Coherent)

    table 2: Core measurement in 45nm SOI expertise.

    determine 5: PowerPC 476 CPU three.6 mm2 difficult core

    7. Design verification via emulation

    functional verification of the PowerPC 476FP CPU, L2 cache and PLB6 bus complex made extensive use of hardware emulation through a custom multi-core FPGA based examine board. besides vastly dashing up the design verification effort, this emulation platform has provided for Linux kernel and gadget driver configuration and testing, and it's proposing for extensive early code building and benchmarking.

    eight. Conclusions

    It has been agreed within the business that the way forward for embedded equipment is multi core. The PPC476 contains three key IP cores; the 1.6GHz CPU, the L2 cache and the PLB6, which mixed together, helps SoC designers to developed embedded equipment with the optimum efficiency. This efficiency is finished with the coherence of information managed by hardware assist.

    9. Acknowledgements

    due to the IBM PowerPC design team for offering suggestions used to prepare this paper.

    References:

    [1] B. Talik “Introduction to the new high-efficiency IBM PowerPC 476FP Core” - Linley Tech Processor Conf Sept 17,09.

    [2] W. Nation “Multicore Processor Cache and Subsystem Design for a excessive-efficiency PowerPC concentrated on Networking and Storage” - Linley Tech Processor Conf Sept 17,09.

    [3] R.Pottier & al "ARM 1176 implementation in SOI 45nm expertise and silicon size" IEEE overseas SoI convention Oct 2009


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