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Pipeline AES S-container Implementation starting with Substitution desk

Valeri Tomashau, LC Engineers, Inc.Rahway, NJ, united states of america

summary :

The SubByte transformation, conducted with the aid of S-field, is essentially the most time ingesting process in superior Encryption standard (AES) algorithm. a look-up table is commonplace for SubByte transformation in AES implementations on FPGAs. when you consider that the S-box is on a important route, the lengthen contributing through the 256-byte seem-up table constrains the highest operating frequency of AES processor and therefore its throughput. to be able to boost the throughput by the use of pipelining it's proposed to decompose the initial 256-byte seem-up-desk into the set of smaller multiplexer-switched look-up tables. suggested approach applies both to FPGA and to ASIC seem-up-desk primarily based AES implementations.


The Rijndael cryptographic algorithm, proposed by Joan Daemen and Vincent Rijmen, has been adopted as a standard (AES) by the us country wide Institute of necessities and technology (NIST) in 2001 [1].

This paper is specializing in the most time consuming step of the AES algorithm. This step is a Non-Linear Byte Substitution that transforms some byte value into a brand new byte value by using an S-box Substitution table [2]. This table incorporates pre-computed inverted values for each of the 256 8-bit numbers (bytes) considered as aspects of the Galois finite field GF(28).

There are two virtually distinct and common methods of S-field hardware implementation. One of those methods consists in immediate the use of of S-container substitution desk, kept in a look-Up table (LUT). The S-container of this classification is quickly, youngsters, it's costly in terms of hardware.

an extra formulation is in response to the calculation of the S field features the use of composite container arithmetic operations. therefore, discovering an inverse in GF(28) is decreased to an inverse in more elementary GF(24) and further multiplications. The formulation goes lower back to Rijmen's recommendation [3]. Such reduction makes it possible for fairly essential hardware implementation of the S-field. although the S-field implementation of this classification is drastically smaller than the LUT-based implementation via enviornment and has the skill to be pipelined, it is greater time and energy drinking.

There are some instant ASIC-implementations of S-box good judgment functions [4, 5]. they're close to LUT-primarily based easy implementations with the aid of prolong and may be pipelined.

A. Hodjat and that i. Verbauwhede [6] have carried out a assessment by area and time between non-pipelined LUT-primarily based S-container implementation and three S-field implementations in accordance with composite field: non-pipelined (single stage), 2 stage pipelined, and three-stage pipelined. they've discovered that the non-pipelined LUT-primarily based implementation is quick (when it comes to throughput) as 3-stage pipeline composite field implementation. besides the fact that children the closing one is 23% smaller in area. additionally, the authors of [7] stated that the LUT-based S-box "cannot be pipelined". In contrast to the above observation, the components counseled during this paper permits pipeline implementation of AES S-box devoid of losing the advantage of the LUT-primarily based strategy.

on the grounds that LUT-based S-field is fast appearing, it would be low in cost to observe the LUT-based mostly method to S-field hardware implementation as the beginning aspect for its further improvement via pipelining. whenever a better AES processor throughput outweighs the enviornment obstacles, recommended system is really helpful.

besides the fact that children the LUT-based mostly S-field cannot be pipelined as such, the linked circuit being explicitly implemented may also be pipelined. one more approach to acquire the pipelined LUT-based S-field is to damage down the preliminary 256-byte look-up-desk into the set of smaller look-up tables. originally, these tables are used to get intermediate outcomes while the closing effect is selected among them by way of multiplexing.

Fig.1. Non-pipeline Xilinx Virtex-5 implementation of an arbitrary 8-variable logic feature (4 6- LUTs are required)


let us take a look on the S-container as a set of eight good judgment capabilities of eight variables. The Sum-of-items (SOP) representation for these features could be simply derived from the S-box substitution table that's nothing but the actuality desk for the set of those services. seeing that the simultaneous optimization of the set of the S-field common sense services isn't a subject of this paper, the sole eight-variable characteristic could be beneath additional consideration. This function will also be defined with the aid of 256-bit appear-up desk, or 256 bit string, or a string of 32 HEX digits.

The aim of multilevel implementation of an 8 variable common sense characteristic is to permit for its pipelining. let us represent the initial feature in the type of superposition of more convenient good judgment capabilities. The advised approach is restricted through accepted Shannon growth as standard skill for the decomposition of an arbitrary good judgment characteristic within the sort of SOP.

chiefly, Xilinx Virtex-5 FPGA [7] is taken as goal hardware. The 6-enter function generator is the basic aspect of this FPGA. each 6-enter feature generator is programmable as a 6-enter seem-Up desk (6-LUT) to put into effect any common sense feature of six variables.

4 6-LUTs together with constructed-in multiplexers F7, F8, and a configurable register form a slice. When configured correctly with the use of the inner multiplexers F7 and F8, a single Virtex-5 slice can implement an arbitrary common sense characteristic of eight variables (Fig. 1). truly, the successive Shannon enlargement (1) of this characteristic by means of two variables is behind the above structure:

here, as an example, SOP10  SOP10 (x1,x2,x3,x4,x5,x6) is the Sum-of-items derived from f(x1,x2,x3,x4,x5,x6,x7,x8) beneath conditions that x7 = 1 and x8 = 0 as indicated by using the decrease indices following the SOP-image.


The structure proven in Fig. 1 contains 4 Xilinx Virtex 5 6-LUTs (one slice) combined with using the developed-in multiplexers F7 and F8. considering that the internal aspects of the slice are inaccessible for inserting pipeline registers, circuit cannot be pipelined. besides the fact that children, it can also be transformed into 2 stage pipeline circuit by using changing the built-in multiplexers F7 and F8 with an additional 6-LUT (Fig. 2).

Fig.2. Two-stage pipeline implementation of an arbitrary eight variable good judgment function (5 6-LUTs are required)

  • on the first stage four SOPs as a consequence of Shannon expansion are calculated with the aid of four 6-LUTs. The effects (S1, S2, S3, S4) are latched in the interior registers of the slice.
  • at the 2d stage 6-LUT performs multiplexing through variables x7 and x8.
  • The sixty four-bit INIT values for the 6-LUTs, that enforce 4 SOPs, can also be retrieved from the feature truth desk. These 4 64-bit strings are really the smaller look-up tables resulted from breaking down the customary 256-bit search for desk.

    compared to the non-pipelined constitution (Fig. 1), just one extra 6-LUT is required to operate multiplexing as an alternative of using internal multiplexers F7 and F8. in order for such constitution to be generated with the aid of the Xilinx Design device, it have to be special explicitly (together with pipeline registers) with using some Xilinx primitives.

    seeing that the inner multiplexers F7 and F8 are not involved, the combinatorial lengthen at the degrees 1 and a couple of is determined fully through the delay of 6-LUT. as a result, stage delay of the circuit proven in Fig. 2 is 68 p.c under the circuit proven in Fig. 1.


    because the immediate entry to 5-LUT has been retained in Xilinx Virtex-5 FPGA, the more productive via lengthen three-stage pipeline circuit will also be developed to implement 8-variable good judgment characteristic (Fig.3). this is feasible as a result of an additional O5-output. It represents an output of 5-LUT bypassing the built-in multiplexer installed on the output of 6-LUT. that is why the stage extend of this circuit is less than the extend of the circuit containing 6-LUTs on the stage.Xilinx primitive LUT6_2 opens an access to the above chance [8].

    The stage extend of the circuit shown in Fig. 3 is 2 instances below the delay of the pure seem-up desk implementation (Fig.1).

  • on the first stage eight SOPs of Shannon expansion are calculated through eight 5-LUTs. The outcomes (S1, S2, S3, S4, S5, S6, S7, S8) are latched within the registers of the slices.
  • at the 2d stage each of 4 5-LUTs performs the alternative between two SOPs together with multiplying the effect with the aid of certainly one of at the same time orthogonal products x6 x7, x6 7, 6 x7, 7 6 . The effects (P1, P2, P3, P4) are latched within the interior registers related to the corresponding 5-LUTs.
  • on the third stage 4-variable OR-feature is carried out. due to the fact the items, outlined above, are mutually orthogonal, just one of them has a non-zero value and therefore OR-feature can be used here.
  • Fig. 3. Three-stage pipeline implementation of an arbitrary eight-variable common sense feature (thirteen 6-LUTs are required


    The equivalent lower in stage lengthen can also be achieved on circumstance that Xilinx Virtex-four sequence FPGA is chosen as goal hardware. on the grounds that this FPGA has 4 input appear-up table because the simple constructing block, the usual 256 bit appear-up desk of eight-variable good judgment feature can also be damaged down into sixteen smaller appear-up tables. The corresponding 4-stage pipeline circuit is shown in Fig. four. None of Xilinx Virtex-4 constructed-in multiplexers is worried. The stage extend of this circuit is completely decided by way of the delay on the 4-enter appear-up table (4-LUT). subsequently, the stage prolong of this circuit is two instances less than the lengthen of a non-pipeline constitution where all built-in multiplexers (F5, F6, F7, F8) are in use.


    Some pipeline architectures are proposed for AES S-box implementation on Xilinx Virtex FPGAs. The essence of the strategy is that the usual certainty desk of each 8-variable common sense function is breaking down into 4, eight, or sixteen actuality tables because of Shannon growth with the aid of two, tree, or four variables. The above small tables fit 6-LUTs, 5-LUTs, or four-LUTs of Xilinx FPGAs. To select the output of 1 or a different small table, further LUTs are used instead of inner multiplexers incorporated within the Xilinx slice.

    Such transformation permits dividing the circuit into few (two, three, or four) pipeline degrees characterized with the aid of smaller prolong than the lengthen of the circuit in keeping with the long-established 256 bit real desk as a unit.

    Throughput of the AES processor in accordance with the proposed S-field architectures may also be 1.5 - 2 times larger than the throughput of the AES processor in accordance with standard appear-up table S-box.

    Some evaluation statistics for Xilinx Virtex-5 and Virtex-four are proven in desk I.

    however the paper refers to Xilinx FPGA, the similar method to S-box speeding-up via pipelining is applicable to ASIC appear-up desk based mostly designs as smartly. here, an effect will also be even stronger because of ASIC's best-grain structure. The most desirable through throughput LUT-primarily based S-container studied in [6] may also be made at least two instances sooner doing nothing however breaking down the initial LUT into set of smaller LUTs according to the cautioned strategy.

    Fig.four. 4-stage pipeline Virtex-four implementation of an arbitrary 8-variable good judgment characteristic devoid of inside multiplexers

    table I. assessment OF FPGA S-box PIPELINE ARCHITECTURES

    S-field architecture (Xilinx Virtex-5, pace Grade-3) 6-LUTs Pipeline Registers Frequency(MHz) Stage prolong (ns) Non-pipelined, Fig. 1 (1-stage) four x 8 = 32 0 438.673 2.280 2-stage pipeline, Fig. 2 (4 +1) x 8 = 40 four x eight + 2* = 34 744.380 1.343 three-stage pipeline, Fig. three (eight+4+1) x 8 = 104 (8+four) x 8+three* = 99 914.746 1.093 (Xilinx Virtex-4, velocity Grade-12) four-LUTs Non-pipelined(1-stage) 16 x 8 = 128 0 425.967 2.348 four-stage pipeline, Fig. four (sixteen+eight+4) = 224 (16+8+4) x 8+6*=230 860.141 1.163

    *) For variables thinking into the Shannon growth to be propagated via a pipeline some added registers are vital.

    within the case of FPGA the benefits of pipelining is considerably reduced because of:

  • high web lengthen, it really is 2-3 instances improved than delay caused via good judgment, and
  • the presence of some unavoidable multiplexers which are rigidly integrated in FPGA.
  • A. When S-field pipelining could be advisable

    it might be well now to ask what effect can also be obtained whereas pipeline S-field is included into the AES rounds. To profit full knowledge from S-box pipelining the AES rounds need to be thoroughly unrolled. in the case of the in part or entirely rolled AES rounds, the gain within the S-box throughput resulted from its pipelining is decreased by unavoidable idle cycles, since the subsequent circular can not be all started except the old one has been comprehensive fully. besides the fact that children within the case of completely rolled AES rounds the use of 8-bit statistics path (the place just one reproduction of the S-box is concerned) can full benefits are received from S-field pipelining. during this case, while the closing 4 bytes of the existing state (the closing column of the state) are still in manner, three bytes of the first column of the subsequent state are already obtainable for processing by the pipelined S-box. in this way we can stay away from any idle cycles on condition that the S-container along side MixColumn has no greater than 4 pipeline ranges.


    The creator is grateful earlier to any individual who will start using this strategy in observe and he is ready to join any R&D crew to enforce the suggested idea in a true hardware.


    [1] "Specification for the advanced Encryption commonplace (AES). Technical report FIPS PUB 197", (NIST), Nov. 2001, [Online]. attainable: http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf.

    [2] B. Gladman, "A Specification for Rijndael, the AES Algorithm." [Online]. Abailable: http://fp.gladman.plus.com/cryptography_technology/rijndael/aesspec.pdf.

    [3] V. Rijmen, "productive implementation of the Rijndael S-container." [Online]. accessible: http://www.comms.scitech.susx.ac.uk/fft/crypto/rijndael-sbox.pdf.

    [4] S. Morioka and A. Satoh, "a 10 Gbps full-AES crypto design with a twisted-BDD S-field structure," IEEE Transactions on differ giant Scale Integration (VLSI) systems, vol. 12, pp. 689-691, July 2004.

    [5] X. Guo, Z. Liu, J. Xing, W. Fan, X. Zou, "Optimized AES crypto desing for instant sensor networks with balanced S-container structure," in Proc. Int. Conf. on Informatics and control technology (ICT 2006), pp. 203-208.

    [6] A. Hodjat and that i. Verbauwhede, "enviornment-throughput alternate-offs for thoroughly pipelined 30 to 70 Gbits/s AES processors," IEEE Transactions on computer systems, vol. 55, pp. 366-372, Apr. 2006.

    [7] "Virtex-5 FPGA user ebook." [Online]. attainable: www.xilinx.com/help/documentation/user_guides/ug190.pdf.

    [8] "Virtex-5 Library e book for HDL Design." [Online]. obtainable: www.xilinx.com/help/documentation/user_guides/ug621.pdf.


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